1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
In recent years, a semiconductor memory device is required in higher operation speed and lower power consumption to realize a highly efficient system. However, as a chip scale became large, the length of a signal line increases so that the increase of a wiring line capacity prevents the high speed operation and the low power consumption. For this reason, in the conventional semiconductor memory device, a memory array is divided into multiple sections to shorten wiring lines such as bit lines and word lines. Thus, the wiring line capacity is reduced so that the high speed operation and the low power consumption are attained.
However, with the further increase of integration, the wiring line capacity increases again.
Also, in a memory system in recent years, because of the improvement of system performance, many input/output lines are used and the power consumption tends to increase in case of driving of data lines.
Moreover, in the conventional semiconductor memory device, a write data signal has the amplitude of a power supply voltage while a read data signal has a small amplitude.
FIG. 1 is a block diagram showing the structure of a conventional semiconductor memory device. Referring to FIG. 1, the conventional semiconductor memory device is composed of a write control circuit and a multiple of memory array sections. The write control circuit is composed of a pair of data lines DLT and DLN, a precharging and equalizing circuit 2, a transfer gate circuit 3, and a data line selecting circuit 4. The data lines DLT and DLN are write data lines for data transfer to a memory block 1. The precharging and equalizing circuit 2 equalizes the data lines DLT and DLN in voltage. The transfer gate circuit 3 connects either of the data lines DLT and DLN to a ground (GND) voltage. The data line selecting circuit 4 controls the transfer gate circuit 3.
The memory block 1 is composed of a memory array 1a, a sense amplifier section 1b, a transfer gate 1c, and a transfer gate 1d. The transfer gate 1c controls the connection of the data lines DLT and DLN to the sense amplifier section 1b in response to a write block selecting signal BSL. The transfer gate 1d controls the sense amplifier section 1b and the memory array 1a in response to a bit line selecting signal YSW.
Next, the operation of the conventional semiconductor memory device will be described with reference to timing charts shown in FIGS. 2A to 2E. The conventional semiconductor memory device is a precharging system by a power supply voltage Vcc.
First, before a writing operation to the memory block 1 is started, a precharge and equalize control signal PDL is set to a low level or a ground (GND) level, as shown in FIG. 2A. As a result, the data lines DLT and DLN are precharged to the power supply voltage VCC. At this time, the bit line portions connected to the sense amplifier section 1b are also precharged to the power supply voltage VCC.
In the writing operation to the memory block 1, the precharge and equalize control signal PDL set to a high level to deactivate the precharging and equalizing circuit 2 for the data lines DLT and DLN, as shown in FIG. 2A. Subsequently, the transfer gate 1c is activated in response to a write block selecting signal BSLn, as shown in FIG. 2B. Thus, the memory block 1 is selected. In this way, the memory block 1 as an object of the writing operation is selected. Then, the data line selecting circuit 4 selects the data lines DLT and DLN in accordance with an input data, and sets one of the data lines DLT and DLN to the GND potential in response to a write enable signal WE shown in FIG. 2C to transfer the input data to the sense amplifier section 1b. Thereafter, the transfer gate 1c is deactivated in accordance with the write block selecting signal BSL, as shown in FIG. 2B. Subsequently, the transfer gate 1d is activated in response to a bit line select signal YSW shown in FIG. 2D. Thus, the memory array 1a and the sense amplifier section 1b are connected so that the data is written in a memory cell.
However, in the conventional semiconductor memory device, the data lines DLT and DLN with large wiring line capacities is driven from the power supply voltage level to the GND level in the writing operation. Therefore, the power consumption is large.
In conjunction with the above description, a dynamic RAM is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-205473). In this reference, switches Q18 and Q19 are provided to connect common source line (PS1) and common data lines (CD1 and /CD1) not only for non-selection period of a memory array (M-ARY1) but also for a selection period. The common source line (PS1) supplies a power supply voltage (Vcc) and a ground voltage (Vss) to a sense amplifier circuit (SA1). The common data lines (CD1 and /CD1) correspond to the memory array (M-ARY1) in which a memory cell to be selected is present. A precharging circuit (PCEQ1) precharges the common source lines (PS1 and NS1) to a predetermined precharge voltage for a non-selection period of the sense amplifier circuit (SA1). When the switches (Q18 and Q19) are turned on, the sense amplifier circuit (SA1) is activated and the common source line (PS1) is increased in voltage from a half precharge level to a Vcc level, the common data lines (CD1 and /CD1) is also increased in voltage.
Also, a write circuit of a random access memory is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-159581). In this reference, when a write control signal (WE) is set to a high level so that a write enable state is established, NMOS transistors (43, 44, 51 and 53) are turned on. When a write data signal D of the high level is supplied, a write data signal Da of a low level and a write data signal Db of the high level are outputted from inverters (41 and 42), respectively. The write data signals Da and Db are transferred to bit lines BLa and BLb via the NMOS transistors 43 and 44, respectively. At this time, the NMOS transistor (52) is turned on in response to the write data signal Db of the high level, so that the voltage of the bit line (BLa) is quickly decreased to the low level via the NMOS transistors (51 and52). In this way, the high speed writing operation of data in the memory cell is attained.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-007569). In this reference, a precharging circuit (6) is activated before a reading operation of a cell data from a memory cell (2) and precharges a bit line BL. A voltage dropping circuit (5) is selectively activated in the precharging operation to the bit line (BL) by the precharging circuit (6) and limits a charge quantity to the bit line (BL). Also, a charge compensating circuit (3) supplies charge to the bit line (BL) for an interval from the time when the charge is injected by the precharging circuit (6) to the time when the charge on the bit line (BL) is discharged by a cell data of the memory cell (2).
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-017183). In this reference, a clamp transistor (Pcr-0) has a threshold voltage Vthp. The clamp transistor (Pcr-0) precharges bit lines BIT-0 and BIT-1 to a precharge voltage (VDD-.vertline.Vthp.vertline.) when transistors Pprc-0 and Pprc-1 are set to a conductive state. A claim transistor Pcr-1 has the same threshold voltage Vthp as the clamp transistor (Pcr-0). Inverters 23 and 24 in a write circuit (3) output the precharge voltage (VDD-.vertline.Vthp.vertline.) as "H" level and the ground voltage as "L" level to input lines (WD-0 and WD-1) based on input data (DIN-0 and DIN-1).
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-134573). In this reference, a main amplifier circuit and a write amplifier circuit operate in a first positive voltage to selectively drive two I/O buses to a second positive voltage for precharge. The main amplifier circuit (130) is composed of a precharging circuit (134) and an activating circuit (132). The precharging circuit (134) separates two I/O buses and precharges the two I/O buses. The activating circuit (132) generates a signal to activate a first section of the main amplifier circuit (130). The signal makes the first section enable such that the two I/O signals are precharged, only when the two I/O buses are separated.